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CAPC is a CPU designed and simulated using LogicWorks4. It is a 16-bit,
accumulator-based processor capable of addressing up to 4k of memory.
As part of Comp212
at Capilano College, every student must create their own version of the
CAPC processor and document their work in the form of an online journal.
3-State Filter - Feb 12, 2005 - The 3S.F.
Device -- download 3S.F. device (right-click
and choose "Save As..")
Journals
Part 1 - Jan 11, 2005 - A clock and a 12-bit
register
Part 2 - Jan 12, 2005 - The special PC register
and the skeletal processor
Part 3 - Jan 13, 2005 - The base processor (HASB)
Part 4 - Jan 20, 2005 - The LDG instruction
Part 5 - Jan 21, 2005 - Replacing the PROM with
RAM
Part 6 - Jan 22, 2005 - The SDG instruction
Part 6 Supplementary - Jan 26, 2005 - The
signal bus
Part 7 - Jan 26, 2005 - The ALU combinational
circuit
Part 8 - Jan 27, 2005 - The JMP and JMI instructions
Part 8 Supplementary - Jan 28, 2005 - The
Operation Logic Unit
Part 9 - Jan 29, 2005 - The ADD instruction
Part 10 - Jan 31, 2005 - The XOR, OR, AND, NOT instructions
Part 11 - Feb 9, 2005 - The ROL and SHR instructions
Part 12 - Jan 31, 2005 - Completion
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