CAPC - Part 2

The special PC register and the skeletal processor

For this lab I constructed a "skeletal processor" which repeatedly copies the PC (program counter) register into the MAR (memory address register) and increments the PC. The copy action is triggered by SC0 (subcycle 0) from the clock and the PC increment is triggered by SC1.

Creating a 12-bit register with an "add1" line for the PC register

The MAR and PC are both 12-bit registers like the one I created in the first lab. However, the PC register needed to have an increment or "add1" line so it could be incremented easily. So I made a special version of the 12-bit register for this purpose.

The first step was to create a 12-bit increment device. My first impression was that I should hook-up half-adders to all the inputs for this device and set the carry-in line on the least-significant bit to one. Then I dropped that idea in favour of the "Adder" devices. Finally, I found the "Incrementer" devices which seemed to present the simplest solution of all.

Next I needed a 2x12 multiplexer to choose the inputs for my PC register from either the external inputs or an internal set given by taking the stored data and feeding it through the incrementer.

With my 12-bit incrementer and multiplexer devices I then proceeded to construct the special PC register which I called "Reg-12 w/add1". To simplify the wiring I used a pair of 12-bit buses in my design.

The skeletal processor

With the previous work down it was now a trivial matter to put together the skeletal processor. In simulation my new machine worked perfectly, requiring only that I clear the PC register before it would get started incrementing. I watched it count up to 3D9h.

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