CAPC - Part 3


The base processor (HASB)

The PROM and two more registers (MBR and IR)

I created a PROM with 12 address lines and 16 bits per word and named it "prom01". Then I created a 16-bit register similar to the 12-bit one from lab #1. The MAR (Memory Address Register) gives an address to the PROM and the PROM outputs the data contained at that address.

I added a 16-bit register and gave the PROM output to it, this is the MBR (Memory Buffer Register). But upon testing the output from the MBR I found that I wasn't getting a signal.

I wasn't sure where the problem was exactly so I slid buses between all the devices and attached hex-displays to them.


This showed me that it was the PROM that wasn't outputting. After I had created "prom01" I had edited the device so I could reposition the pins and have the label appear horizontal like the other devices.

Apparently this disables the PROM, so I was forced to re-create it and then leave it as is (notice that in later designs below the label is vertical).


Next I added the 16-bit IR (Instruction Register) and then wrote the following table to clarify the timing in my mind before doing the wiring:
Timing Sequence
SC0 : send > PC
SC0+3 : load > MAR
SC1 : add1 > PC
SC1+3 : load > MBR
SC2 : send > MBR
SC2+3 : load > IR

The Unstartable Problem

This is the problem that haunted my development of the run flip-flop.

When the processor has not been initialized the halt line coming from the machine instruction decoder has no signal. Unfortunately, if the halt line input of the run flip-flop has no signal then its run output line will also have no signal regardless of the signal coming from the powerOn line.

In other words, you can't start the machine running if it's never been run before and you can't run it if you can't start it.

What I needed was a way to take the input halt line and have it be zero for either a zero signal or for no signal. But I never found a way to do this.

The run flip-flop

I needed what amounts to being the power switch for my processor. A device with two input lines, Power-On and HALT and one output line RUN. When RUN is set to zero it ignores the HALT line and waits for a rising-edge signal from the Power-On line, then sets RUN to sending a signal of one. Then ignores the Power-On line and waits for a rising-edge signal from the HALT line.

SR-type run flip-flop
D-type run flip-flop

I tinkered with several different types of flip-flops and finally settled on using an SR-type with rising-edge detectors on the device inputs. However, much tinkering I was still unable to make my RunFF device solve the unstartable problem (see sidebar).

I decided to look at alternate solutions and found a D-type flip-flop based RunFF in the journals of a student from last year. Unfortunately this did not solve the unstartable problem, but I switched to using it anyways since it was claimed to be the "correct" solution.

I finally ended up simply initializing the processor manually. I placed a binary switch on the halt line of the run flip-flop until the processor had started running, then I paused the simulation and rewired the halt line to the decoder.

Afterwards I sent a branch of the run line down through a rising-edge detector and into the clear line for the PC register (Program Counter) so that activation of the run line resets the program counter to instruction zero.

Conclusion

The machine runs correctly, processing instructions until reaching the HALT instruction and then halting the machine. At which point the powerOn switch will restart it and it will repeat execution of the PROM program.

I added a secondary bus which I named the "OP-CODE DISPLAY BUS" so that I could see the current instruction.

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